A scalable architecture for ordered parallelism

Author:

Jeffrey Mark C.1,Subramanian Suvinay1,Yan Cong1,Emer Joel2,Sanchez Daniel1

Affiliation:

1. MIT CSAIL

2. NVIDIA / MIT CSAIL

Funder

C-FAR, one of six SRC STARnet centers by MARCO and DARPA

NSF

Publisher

ACM

Reference78 articles.

1. "9th DIMACS Implementation Challenge: Shortest Paths " 2006. "9th DIMACS Implementation Challenge: Shortest Paths " 2006.

2. The SprayList: a scalable relaxed priority queue

3. 4096×128 ternary CAM datasheet (28nm) Analog Bits 2011. 4096×128 ternary CAM datasheet (28nm) Analog Bits 2011.

4. Dynamic dependency analysis of ordinary programs

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