A scalable architecture for ordered parallelism-Reference-Cited by-同舟云学术

A scalable architecture for ordered parallelism

Published:2015-12-05 Issue: Volume: Page:
ISSN:
Container-title:Proceedings of the 48th International Symposium on Microarchitecture
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Author:

Jeffrey Mark C.¹,Subramanian Suvinay¹,Yan Cong¹,Emer Joel²,Sanchez Daniel¹

Affiliation:

1. MIT CSAIL

2. NVIDIA / MIT CSAIL

Funder

C-FAR, one of six SRC STARnet centers by MARCO and DARPA

NSF

Publisher

ACM

Link

Reference78 articles.

1. "9th DIMACS Implementation Challenge: Shortest Paths " 2006. "9th DIMACS Implementation Challenge: Shortest Paths " 2006.

3. 4096×128 ternary CAM datasheet (28nm) Analog Bits 2011. 4096×128 ternary CAM datasheet (28nm) Analog Bits 2011.

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