A Distributed Hardware Monitoring System for Runtime Verification on Multi-Tile MPSoCs
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Published:2021-03-31
Issue:1
Volume:18
Page:1-25
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ISSN:1544-3566
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Container-title:ACM Transactions on Architecture and Code Optimization
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language:en
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Short-container-title:ACM Trans. Archit. Code Optim.
Author:
Mettler Marcel1ORCID,
Mueller-Gritschneder Daniel1,
Schlichtmann Ulf1
Affiliation:
1. Chair of EDA, Technical University of Munich
Abstract
Exhaustive verification techniques do not scale with the complexity of today’s multi-tile Multi-processor Systems-on-chip (MPSoCs). Hence, runtime verification (RV) has emerged as a complementary method, which verifies the correct behavior of applications executed on the MPSoC during runtime.
In this article, we propose a decentralized monitoring architecture for large-scale multi-tile MPSoCs. In order to minimize performance and power overhead for RV, we propose a lightweight and non-intrusive hardware solution. It features a new specialized tracing interconnect that distributes and sorts detected events according to their timestamps. Each tile monitor has a consistent view on a globally sorted trace of events on which the behavior of the target application can be verified using logical and timing requirements. Furthermore, we propose an integer linear programming-based algorithm for the assignment of requirements to monitors to exploit the local resources best. The monitoring architecture is demonstrated for a four-tiled MPSoC with 20 cores implemented on a Virtex-7 field-programmable gate array (FPGA).
Funder
Deutsche Forschungsgemeinschaft
Publisher
Association for Computing Machinery (ACM)
Subject
Hardware and Architecture,Information Systems,Software
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