Author:
Hamamoto Koichi,Hashimoto Masanori,Mitsuyama Yukio,Onoye Takao
Cited by
3 articles.
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1. A Floorplan Aware High-Level Synthesis Algorithm with Body Biasing for Delay Variation Compensation;IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences;2017
2. Ultra Low Voltage Subthreshold Circuit Design;IEICE ESS Fundamentals Review;2013
3. A Body Bias Clustering Method for Low Test-Cost Post-Silicon Tuning;IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences;2012