Improving 3D NAND Flash Memory Lifetime by Tolerating Early Retention Loss and Process Variation

Author:

Luo Yixin1,Ghose Saugata1,Cai Yu2,Haratsch Erich F.3,Mutlu Onur4

Affiliation:

1. Carnegie Mellon University, Pittsburgh, PA, USA

2. Carnegie Mellon University, San Jose, CA, USA

3. Seagate Technology, Fremont, CA, USA

4. ETH Zürich & Carnegie Mellon University, Zürich, Switzerland

Funder

Samsung

Huawei

Seagate

Intel

Publisher

ACM

Cited by 33 articles. 订阅此论文施引文献 订阅此论文施引文献,注册后可以免费订阅5篇论文的施引文献,订阅后可以查看论文全部施引文献

1. LDPC Level Prediction Toward Read Performance of High-Density Flash Memories;IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems;2023-10

2. Retention Leveling: Leverage Retention Refreshing and Wear Leveling Techniques to Enhance Flash Reliability with the Awareness of Temperature;2023 IEEE 12th Non-Volatile Memory Systems and Applications Symposium (NVMSA);2023-08

3. Main memory controller with multiple media technologies for big data workloads;Journal of Big Data;2023-05-22

4. Towards LDPC Read Performance of 3D Flash Memories with Layer-induced Error Characteristics;ACM Transactions on Design Automation of Electronic Systems;2023-04-18

5. Enhancing Polar Codes Efficiency on 3D Flash Memory by Exploiting Multiple Error Variations;Proceedings of the 38th ACM/SIGAPP Symposium on Applied Computing;2023-03-27

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