Mapping-Aware Constrained Scheduling for LUT-Based FPGAs-Reference-Cited by-同舟云学术

Mapping-Aware Constrained Scheduling for LUT-Based FPGAs

Published:2015-02-22 Issue: Volume: Page:
ISSN:
Container-title:Proceedings of the 2015 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays
language:
Short-container-title:

Author:

Tan Mingxing¹,Dai Steve¹,Gupta Udit¹,Zhang Zhiru¹

Affiliation:

1. Cornell University, Ithaca, NY, USA

Funder

NSF

Publisher

ACM

Link

https://dl.acm.org/doi/pdf/10.1145/2684746.2689063

Reference31 articles.

1. A comparison of list schedules for parallel processing systems

2. A Comparative Evaluation of High-Level Hardware Synthesis Using Reed–Solomon Decoder

3. An Asynchronous FPGA Block with Its Tech-Mapping Algorithm Dedicated to Security Applications

4. A. Canis S. Brown and J. Anderson. Modulo SDC Scheduling with Recurrence Minimization in High-Level Synthesis. Int'l Conf. on Field Programmable Logic and Applications (FPL) pages 1--8 2014. A. Canis S. Brown and J. Anderson. Modulo SDC Scheduling with Recurrence Minimization in High-Level Synthesis. Int'l Conf. on Field Programmable Logic and Applications (FPL) pages 1--8 2014.

5. D. Chen and J. Cong. DAOmap: A Depth-Optimal Area Optimization Mapping Algorithm for FPGA Designs. Int'l Conf. on Computer-Aided Design (ICCAD) pages 752--759 2004. 10.1109/ICCAD.2004.1382677 D. Chen and J. Cong. DAOmap: A Depth-Optimal Area Optimization Mapping Algorithm for FPGA Designs. Int'l Conf. on Computer-Aided Design (ICCAD) pages 752--759 2004. 10.1109/ICCAD.2004.1382677

Cited by 14 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. Hyperblock Scheduling for Verified High-Level Synthesis;Proceedings of the ACM on Programming Languages;2024-06-20

2. Subgraph Extraction-Based Feedback-Guided Iterative Scheduling for HLS;2024 Design, Automation & Test in Europe Conference & Exhibition (DATE);2024-03-25

3. High-Level Synthesis;FPGA EDA;2024

4. TAPA: A Scalable Task-parallel Dataflow Programming Framework for Modern FPGAs with Co-optimization of HLS and Physical Design;ACM Transactions on Reconfigurable Technology and Systems;2023-12-05

5. MapBuf: Simultaneous Technology Mapping and Buffer Insertion for HLS Performance Optimization;2023 IEEE/ACM International Conference on Computer Aided Design (ICCAD);2023-10-28