Clock-Aware FPGA Placement Contest-Reference-Cited by-同舟云学术

Clock-Aware FPGA Placement Contest

Published:2017-03-19 Issue: Volume: Page:
ISSN:
Container-title:Proceedings of the 2017 ACM on International Symposium on Physical Design
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Author:

Yang Stephen¹,Mulpuri Chandra¹,Reddy Sainath¹,Kalase Meghraj¹,Dasasathyan Srinivasan¹,Dehkordi Mehrdad E.¹,Tom Marvin¹,Aggarwal Rajat¹

Affiliation:

1. Xilinx Inc., San Jose, CA, USA

Publisher

ACM

Link

https://dl.acm.org/doi/pdf/10.1145/3036669.3038241

Reference11 articles.

1. FPGA place & route challenges

2. Routability-Driven FPGA Placement Contest

3. Xilinx "UltraScale Architecture" http://www.xilinx.com/products/technology/ultrascale.html Xilinx "UltraScale Architecture" http://www.xilinx.com/products/technology/ultrascale.html

4. Xilinx "Virtex UltraScale FPGAs" http://www.xilinx.com/publications/prod_mktg/ultrascalevirtex-product-table Xilinx "Virtex UltraScale FPGAs" http://www.xilinx.com/publications/prod_mktg/ultrascalevirtex-product-table

5. Xilinx "UltraScale Architecture Configurable Logic Block User Guide" http://www.xilinx.com/support/documentation/user_guides/ug574-ultrascale-clb.pdf Xilinx "UltraScale Architecture Configurable Logic Block User Guide" http://www.xilinx.com/support/documentation/user_guides/ug574-ultrascale-clb.pdf

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