Pin Accessibility-Driven Detailed Placement Refinement
Author:
Affiliation:
1. Iowa State University, Ames, IA, USA
2. National Tsing Hua University, Hsinchu, Taiwan Roc
Publisher
ACM
Link
https://dl.acm.org/doi/pdf/10.1145/3036669.3036679
Reference19 articles.
1. Can pin access limit the footprint scaling?
2. Self-aligned double patterning aware pin access and standard cell layout co-optimization
3. PARR
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3. Design of Digital Integrated Circuits by Improving the Characteristics of Digital Cells;Machine Learning-based Design and Optimization of High-Speed Circuits;2023-12-31
4. Pin Accessibility Improvement with Hit-Point Distribution Metrics for Sub-4nm Standard Cell;2023 IEEE 36th International System-on-Chip Conference (SOCC);2023-09-05
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