Age-aware Logic and Memory Co-Placement for RRAM-FPGAs
Author:
Affiliation:
1. University of Delaware
2. Oklahoma State University
Funder
National Science Foundation
Publisher
ACM
Link
https://dl.acm.org/doi/pdf/10.1145/3061639.3062198
Reference19 articles.
1. UltraScale Architecture and Product Overview Xilinx 2016. UltraScale Architecture and Product Overview Xilinx 2016.
2. Measuring the Gap Between FPGAs and ASICs
3. FPGA-RPI: A Novel FPGA Architecture With RRAM-Based Programmable Interconnects
4. STRAP: Stress-aware placement for aging mitigation in runtime reconfigurable architectures;Zhang H.;ICCAD,2015
5. VTR 7.0
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