Partition and place finite element model on wafer-scale engine-Reference-Cited by-同舟云学术

Partition and place finite element model on wafer-scale engine

Published:2022-07-10 Issue: Volume: Page:
ISSN:
Container-title:Proceedings of the 59th ACM/IEEE Design Automation Conference
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Author:

Liu Jinwei¹,Zhang Xiaopeng¹,Lin Shiju¹,Zang Xinshi¹,Chen Jingsong¹,Jiang Bentian¹,Wong Martin D. F.¹,Young Evangeline F. Y.¹

Affiliation:

1. CUHK

Publisher

ACM

Link

https://dl.acm.org/doi/pdf/10.1145/3489517.3530565

Reference8 articles.

1. FPGA placement and routing

2. Zhisong Fu et al. 2014. Architecting the finite element method pipeline for the GPU. Journal of computational and applied mathematics (2014). Zhisong Fu et al. 2014. Architecting the finite element method pipeline for the GPU. Journal of computational and applied mathematics (2014).

3. Patrick Groeneveld et al. 2021 . ISPD 2021 Wafer-Scale Physics Modeling Contest: A New Frontier for Partitioning, Placement and Routing. In Proceedings of the 2021 International Symposium on Physical Design. Patrick Groeneveld et al. 2021. ISPD 2021 Wafer-Scale Physics Modeling Contest: A New Frontier for Partitioning, Placement and Routing. In Proceedings of the 2021 International Symposium on Physical Design.

4. Zhuolun He et al. 2021. Physical synthesis for advanced neural network processors . In 2021 26th Asia and South Pacific Design Automation Conference (ASP-DAC). IEEE. Zhuolun He et al. 2021. Physical synthesis for advanced neural network processors. In 2021 26th Asia and South Pacific Design Automation Conference (ASP-DAC). IEEE.

5. Bentian Jiang et al. 2020. CU. POKer: placing DNNs on wafer-scale AI accelerator with optimal kernel sizing . In Proceedings of the 39th International Conference on Computer-Aided Design. Bentian Jiang et al. 2020. CU. POKer: placing DNNs on wafer-scale AI accelerator with optimal kernel sizing. In Proceedings of the 39th International Conference on Computer-Aided Design.