Optimizing instruction TLB energy using software and hardware techniques

Author:

Kadayif I.1,Sivasubramaniam A.2,Kandemir M.2,Kandiraju G.2,Chen G.2

Affiliation:

1. Canakkale Onsekiz Mart University, Canakkale, Turkey

2. The Pennsylvania State University, University Park, PA

Abstract

Power consumption and power density for the Translation Look-aside Buffer (TLB) are important considerations not only in its design, but can have a consequence on cache design as well. After pointing out the importance of instruction TLB (iTLB) power optimization, this article embarks on a new philosophy for reducing the number of accesses to this structure. The overall idea is to keep a translation currently being used in a register and avoid going to the iTLB as far as possible---until there is a page change. We propose four different approaches for achieving this, and experimentally demonstrate that one of these schemes that uses a combination of compiler and hardware enhancements can reduce iTLB dynamic power by over 85% in most cases.The proposed approaches can work with different instruction-cache (iL1) lookup mechanisms and achieve significant iTLB power savings without compromising on performance. Their importance grows with higher iL1 miss rates and larger page sizes. They can work very well with large iTLB structures that can possibly consume more power and take longer to lookup, without the iTLB getting into the common case. Further, we also experimentally demonstrate that they can provide performance savings for virtually indexed, virtually tagged iL1 caches, and can even make physically indexed, physically tagged iL1 caches a possible choice for implementation.

Publisher

Association for Computing Machinery (ACM)

Subject

Electrical and Electronic Engineering,Computer Graphics and Computer-Aided Design,Computer Science Applications

Cited by 6 articles. 订阅此论文施引文献 订阅此论文施引文献,注册后可以免费订阅5篇论文的施引文献,订阅后可以查看论文全部施引文献

1. A survey of techniques for architecting TLBs;Concurrency and Computation: Practice and Experience;2016-12-22

2. A Leakage Efficient Data TLB Design for Embedded Processors;IEICE Transactions on Information and Systems;2011

3. A Leakage Efficient Instruction TLB Design for Embedded Processors;IEICE Transactions on Information and Systems;2011

4. Control Mechanism for Low Power Embedded TLB;Lecture Notes in Electrical Engineering;2011

5. Code Transformations for TLB Power Reduction;International Journal of Parallel Programming;2010-01-21

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