Cache design trade-offs for power and performance optimization

Author:

Su Ching-Long,Despain Alvin M.

Publisher

ACM Press

Cited by 46 articles. 订阅此论文施引文献 订阅此论文施引文献,注册后可以免费订阅5篇论文的施引文献,订阅后可以查看论文全部施引文献

1. Decoupling address generation from loads and stores to improve data access energy efficiency;ACM SIGPLAN Notices;2018-12-07

2. Decoupling address generation from loads and stores to improve data access energy efficiency;Proceedings of the 19th ACM SIGPLAN/SIGBED International Conference on Languages, Compilers, and Tools for Embedded Systems;2018-06-19

3. Improvement of Data Utilization Efficiency for Cache Memory by Compressing Frequent Bit Sequences;IEICE Transactions on Electronics;2016

4. Redesigning a tagless access buffer to require minimal ISA changes;Proceedings of the International Conference on Compilers, Architectures and Synthesis for Embedded Systems - CASES '16;2016

5. Design Space Exploration Using Cycle Accurate Simulator;Innovative Research and Applications in Next-Generation High Performance Computing;2016

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