Improvement of Data Utilization Efficiency for Cache Memory by Compressing Frequent Bit Sequences-Reference-Cited by-同舟云学术

Improvement of Data Utilization Efficiency for Cache Memory by Compressing Frequent Bit Sequences

Published:2016 Issue:8 Volume:E99.C Page:936-946
ISSN:0916-8524
Container-title:IEICE Transactions on Electronics
language:en
Short-container-title:IEICE Trans. Electron.

Author:

KOBAYASHI Ryotaro¹,KANEKO Ikumi¹,SHIMADA Hajime²

Affiliation:

1. Graduate School of Engineering, Toyohashi University of Technology

2. Nagoya University

Publisher

Institute of Electronics, Information and Communications Engineers (IEICE)

Subject

Electrical and Electronic Engineering,Electronic, Optical and Magnetic Materials

Link

https://www.jstage.jst.go.jp/article/transele/E99.C/8/E99.C_936/_pdf

Reference20 articles.

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3. [3] N. Suzuki, M. Urahama, and Y. Tokunaga, “ARM946E-S core low-power desing method (device articles),” Oki Technical Review, vol.72, no.3, pp.52-55, 2005.

4. [4] K. Oka, H. Sasaki, and K. Inoue, “Line sharing cache: Exploring cache capacity with frequent line value locality,” Proceedings of the 2013 18th Asia and South Pacific Design Automation Conference, pp.669-674, 2013.

5. [5] J. Yang, Y. Zhang, and R. Gupta, “Frequent value compression in data caches,” Proceedings of the 33rd Annual ACM/IEEE International Symposium on Microarchitecture, pp.258-265, 2000.