Author:
Burger Doug,Goodman James R.,Kägi Alain
Cited by
77 articles.
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1. A Fully Digital Relaxation-Aware Analog Programming Technique for HfOx RRAM Arrays;IEEE Transactions on Circuits and Systems II: Express Briefs;2024-08
2. ROMA: A Reconfigurable On-chip Memory Architecture for Multi-core Accelerators;2023 IEEE International Conference on High Performance Computing & Communications, Data Science & Systems, Smart City & Dependability in Sensor, Cloud & Big Data Systems & Application (HPCC/DSS/SmartCity/DependSys);2023-12-17
3. Future Scaling of Memory Hierarchy for Tensor Cores and Eliminating Redundant Shared Memory Traffic Using Inter-Warp Multicasting;IEEE Transactions on Computers;2022
4. A performance & power comparison of modern high-speed DRAM architectures;Proceedings of the International Symposium on Memory Systems;2018-10
5. Dynamic fine-grained sparse memory accesses;Proceedings of the International Symposium on Memory Systems;2018-10