Author:
Cong Jason,Liu Bin,Luo Guojie,Prabhakar Raghu
Cited by
6 articles.
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1. The shift-left design paradigm of EDA: progress and challenges;SCIENTIA SINICA Informationis;2024-01-01
2. High Level Congestion Detection from C/C++ Source Code for High Level Synthesis;IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences;2020-12-01
3. Interconnection-Delay and Clock-Skew Estimate Modelings for Floorplan-Driven High-Level Synthesis Targeting FPGA Designs;IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences;2016
4. Physically aware high level synthesis design flow;Proceedings of the 52nd Annual Design Automation Conference;2015-06-07
5. Mapping-Aware Constrained Scheduling for LUT-Based FPGAs;Proceedings of the 2015 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays;2015-02-22