Physically aware high level synthesis design flow-Reference-Cited by-同舟云学术

Physically aware high level synthesis design flow

Published:2015-06-07 Issue: Volume: Page:
ISSN:
Container-title:Proceedings of the 52nd Annual Design Automation Conference
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Author:

Tatsuoka Masato¹,Watanabe Ryosuke¹,Otsuka Tatsushi¹,Hasegawa Takashi¹,Zhu Qiang²,Okamura Ryosuke²,Li Xingri²,Takabatake Tsuyoshi²

Affiliation:

1. Socionext, Inc.

2. Cadence Design Systems, Japan

Publisher

ACM

Link

https://dl.acm.org/doi/pdf/10.1145/2744769.2744893

Reference14 articles.

1. Congestion Aware High Level Synthesis Combined with Floorplanning

2. Towards layout-friendly high-level synthesis

3. A metric for layout-friendly microarchitecture optimization in high-level synthesis

4. Layout-driven resource sharing in high-level synthesis

5. M. Clarke D. Hammerschlag M. Rardon and A. Sood. Eliminating Routing Congestion Issues with Logic Synthesis. Cadence White Paper http://www.cadence.com/rl/resources/white_papers/routing_congestion_wp.pdf M. Clarke D. Hammerschlag M. Rardon and A. Sood. Eliminating Routing Congestion Issues with Logic Synthesis. Cadence White Paper http://www.cadence.com/rl/resources/white_papers/routing_congestion_wp.pdf

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