Locality analysis to control dynamically way-adaptable caches

Author:

Kobayashi Hiroaki1,Kotera Isao1,Takizawa Hiroyuki1

Affiliation:

1. Tohoku University, Sendai, Japan

Abstract

This paper presents a control mechanism for dynamically way-adaptable caches. The mechanism uses the local and global information about the locality of reference during execution. As the local information, the cache access pattern is evaluated based on the statistics of the LRU (Least-Recently Used) states of cache entries referenced. If the memory accesses are concentrated on and near the most recently used entries, the mechanism knows that the locality of reference is very high and there is room to decrease the number of ways activated to fit the current locality. On the other hand, if the accesses are widely distributed from the most recently used entries to the least recently used ones, the mechanism understands that more ways are needed to improve the performance as long as the resources are available. In addition, to examine the global behavior of the locality of reference, an n-bit state machine like n-bit branch predictors is introduced into the mechanism. The state machine traces a sequence of cache resizing requests and evaluates its stability across the execution time. Therefore, the state machine helps the mechanism avoid unstable actions for enabling/disabling cache ways when the locality shows the highly irregular behavior. The experimental results indicate that an n-bit asymmetric state machine using the LRU status information works well to appropriately control cache ways even in the case of the benchmarks with highly-irregular access behaviors in cache references.

Publisher

Association for Computing Machinery (ACM)

Reference14 articles.

1. Compaq Alpha 21264 Microprocessor Hardware Reference Manual. Technical report Compaq Computer Corporation 1999. Compaq Alpha 21264 Microprocessor Hardware Reference Manual. Technical report Compaq Computer Corporation 1999.

2. Intel Corporation. Intel StrongARM SA-110 Microrprocessor. http://www.intel.com/design/strong/sa_110doc.htm 1999. Intel Corporation. Intel StrongARM SA-110 Microrprocessor. http://www.intel.com/design/strong/sa_110doc.htm 1999.

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