A Hardware Pipeline with High Energy and Resource Efficiency for FMM Acceleration

Author:

Huang Tian1,Zhu Yongxin1ORCID,Ha Yajun2,Wang Xu1,Qiu Meikang3ORCID

Affiliation:

1. School of Microelectronics, Shanghai Jiao Tong University, Shanghai, China

2. School of Information Science and Technology, ShanghaiTech University, Shanghai, China

3. College of Computer Science and Software Engineering, Shenzhen University, Shanghai, China

Abstract

The fast multipole method (FMM) is a promising mathematical technique that accelerates the calculation of long-ranged forces in the large-sized n-body problem. Existing implementations of the FMM on general-purpose processors are energy and resource inefficient. To mitigate these issues, we propose a hardware pipeline that accelerates three key FMM steps. The pipeline improves energy efficiency by exploiting fine-granularity parallelism of the FMM. We reuse the pipeline for different FMM steps to reduce resource usage by 66%. Compared to the state-of-the-art implementations on CPUs and GPUs, our implementation requires 15% less energy and delivers 2.61 times more floating-point operations.

Publisher

Association for Computing Machinery (ACM)

Subject

Hardware and Architecture,Software

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