A hard real-time capable multi-core SMT processor-Reference-Cited by-同舟云学术

A hard real-time capable multi-core SMT processor

Published:2013-03-10 Issue:3 Volume:12 Page:1-26
ISSN:1539-9087
Container-title:ACM Transactions on Embedded Computing Systems
language:en
Short-container-title:ACM Trans. Embed. Comput. Syst.

Author:

Paolieri Marco¹,Mische Jörg²,Metzlaff Stefan²,Gerdes Mike²,Quiñones Eduardo³,Uhrig Sascha⁴,Ungerer Theo²,Cazorla Francisco J.⁵

Affiliation:

1. Barcelona Supercomputing Center, Universitat Politècnica de Catalunya

2. University of Augsburg

3. Barcelona Supercomputing Center

4. Technical University of Dortmund

5. Barcelona Supercomputing Center, Spanish National Research Council

Abstract

Hard real-time applications in safety critical domains require high performance and time analyzability. Multi-core processors are an answer to these demands, however task interferences make multi-cores more difficult to analyze from a worst-case execution time point of view than single-core processors. We propose a multi-core SMT processor that ensures a bounded maximum delay a task can suffer due to inter-task interferences. Multiple hard real-time tasks can be executed on different cores together with additional non real-time tasks. Our evaluation shows that the proposed MERASA multi-core provides predictability for hard real-time tasks and also high performance for non hard real-time tasks.

Publisher

Association for Computing Machinery (ACM)

Subject

Hardware and Architecture,Software

Link

https://dl.acm.org/doi/pdf/10.1145/2442116.2442129

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