Cell library characterization using machine learning for design technology co-optimization
Author:
Affiliation:
1. Karlsruhe Institute of Technology, Germany
2. Indian Institute of Technology Kanpur, India
3. University of Stuttgart, Germany
Funder
U.S. Office of Naval Research (ONR)
Publisher
ACM
Link
https://dl.acm.org/doi/pdf/10.1145/3400302.3415713
Reference24 articles.
1. Designing 0.5 V 5-nm HP and 0.23 V 5-nm LP NC-FinFETs With Improved ${I}_{ \mathrm{\scriptscriptstyle OFF}}$ Sensitivity in Presence of Parasitic Capacitance
2. NCFET Design Considering Maximum Interface Electric Field
3. Negative Capacitance Transistor to Address the Fundamental Limitations in Technology Scaling: Processor Performance
4. Unveiling the Impact of IR-Drop on Performance Gain in NCFET-Based Processors
5. Analysis of Negative-Capacitance Germanium FinFET With the Presence of Fixed Trap Charges
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