Fast Cell Library Characterization for Design Technology Co-Optimization Based on Graph Neural Networks
Author:
Affiliation:
1. Shanghai Jiao Tong University,Shanghai,China
Publisher
IEEE
Link
http://xplorestaging.ieee.org/ielx7/10473777/10473787/10473933.pdf?arnumber=10473933
Reference24 articles.
1. Reliable on-chip systems in the nano-era
2. High Performance 4nm FinFET Platform (4LPE) with Novel Advanced Transistor Level DTCO for Dual-CPP/HP-HD Standard Cells
3. Exploring Logic Optimizations with Reinforcement Learning and Graph Convolutional Network
4. Introducing 2D-FETs in Device Scaling Roadmap using DTCO
5. A Novel Framework for DTCO: Fast and Automatic Routability Assessment with Machine Learning for Sub-3nm Technology Options;Chidambaram
Cited by 1 articles. 订阅此论文施引文献 订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献
1. Fast Design Technology Co-Optimization Framework for Emerging Technology with Hierarchical Graph Embedding;2024 2nd International Symposium of Electronics Design Automation (ISEDA);2024-05-10
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