Load-Aware Redundant Via Insertion for Electromigration Avoidance
Author:
Affiliation:
1. Institute of Electromechanical and Electronic Design (IFTE), Dresden, Germany
Publisher
ACM
Link
https://dl.acm.org/doi/pdf/10.1145/2872334.2872355
Reference26 articles.
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2. Cut Optimization for Redundant Via Insertion in Self-Aligned Double Patterning;ACM Transactions on Design Automation of Electronic Systems;2019-11-14
3. Electromigration Analysis of VLSI Circuits Using the Finite Element Method;VLSI-SoC: Opportunities and Challenges Beyond the Internet of Things;2019
4. The need and opportunities of electromigration-aware integrated circuit design;Proceedings of the International Conference on Computer-Aided Design;2018-11-05
5. Electromigration- and Parasitic-Aware ILP-Based Analog Router;IEEE Transactions on Very Large Scale Integration (VLSI) Systems;2018-10
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