Power and clock gating modelling in coarse grained reconfigurable systems
Author:
Affiliation:
1. University of Cagliari
2. University of Sassari PolComIng
Publisher
ACM
Link
https://dl.acm.org/doi/pdf/10.1145/2903150.2911713
Reference32 articles.
1. Integrated Kernel Partitioning and Scheduling for Coarse-Grained Reconfigurable Arrays
2. Coarse grain clock gating of streaming applications in programmable logic implementations
3. Reconfigurable Coprocessor for Multimedia Application Domain
4. FALPEM: Framework for Architectural-Level Power Estimation and Optimization for Large Memory Sub-Systems
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