Profiling-Driven Multi-Cycling in FPGA High-Level Synthesis-Reference-Cited by-同舟云学术

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Profiling-Driven Multi-Cycling in FPGA High-Level Synthesis

Published:2015 Issue: Volume: Page:
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Container-title:Design, Automation & Test in Europe Conference & Exhibition (DATE), 2015
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Author:

Hadjis Stefan,Canis Andrew,Sobue Ryoya,Hara-Azumi Yuko,Tomiyama Hiroyuki,Anderson Jason

Publisher

IEEE Conference Publications

Cited by 8 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. Using Multiple Clocks in Highlevel Synthesis to overcome unbalanced clock cycles;2023 IEEE 16th International Symposium on Embedded Multicore/Many-core Systems-on-Chip (MCSoC);2023-12-18

2. Adaptive Clock Management of HLS-generated Circuits on FPGAs;ACM Transactions on Reconfigurable Technology and Systems;2022-12-14

3. Accelerator Design with High-Level Synthesis;Handbook of Computer Architecture;2022

4. A Survey on Performance Optimization of High-Level Synthesis Tools;Journal of Computer Science and Technology;2020-05

5. An FPGA comparative study of high‐level and low‐level combined designs for HEVC intra, inverse quantization, and IDCT/IDST 2D modules;International Journal of Circuit Theory and Applications;2020-04-14

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