Proposal of High-Density Packaging Construction and Conductive Pattern Forming Method on Vertical Wall Using Spray Coating Technology
Author:
Affiliation:
1. Department of I.M.S.E, Kagawa University
2. Toyota Technological Institute
3. AOI Electronics co., Ltd.
4. U-mic. Co., Ltd.
Publisher
Institute of Electrical Engineers of Japan (IEE Japan)
Subject
Electrical and Electronic Engineering,Mechanical Engineering
Link
http://www.jstage.jst.go.jp/article/ieejsmas/131/1/131_1_40/_pdf
Reference11 articles.
1. (1) http://panasonic-denko.co.jp/ac/j/special/miptec/series/03/index.jsp
2. (2) S. Morishita, J. H. Kim, F. Marty, Y. Li, A. J. Walton, and Y. Mita : “A three-dimensional Silicon shadow mask for patterning on trenches with vertical walls”, Transducers 2009, Denver, USA, pp. 1608-1611 (2009)
3. (3) G. H. Kang, K. Y. No, and G. M. Kim : “Fabrication of microchannel with electrodes on side wall”, International Journal of Modern Physics B, Vol. 20, No. 25, pp. 4493-4498 (2006)
4. (4) M. Sasaki, S. Nogawa, and K. Hane : “Spray coating of photoresist for three dimensional micromachining”, Trans. IEE Jpn., Vol. 122-E, No. 5, pp. 235-243 (2002)
5. (5) V. K. Singh, M. Sasaki, J. H. Song, and K. Hane : “Heating Effect on Photoresist in Spray Coating Technique for Three-Dimensional Lithography”, Jpn. J. Appl. Phys., Vol. 42, Part 1, No. 6B, pp. 4027-4030 (2003)
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