Formally verified synthesis of combinational CMOS circuits-Reference-Cited by-同舟云学术

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Formally verified synthesis of combinational CMOS circuits

Published:1991-06 Issue:3 Volume:11 Page:235-250
ISSN:0167-9260
Container-title:Integration
language:en
Short-container-title:Integration

Author:

Basin David A.,Brown Geoffrey M.,Leeser Miriam E.

Publisher

Elsevier BV

Subject

Electrical and Electronic Engineering,Hardware and Architecture,Software

Reference24 articles.

1. Implementing problem solving environments in constructive type theory;Basin,1989

2. Logic Minimization Algorithms for VLSI Synthesis;Brayton,1986

3. MOSSIM: a switch-level simulator for MOS LSI;Bryant,1981

4. A switch-level simulation model for integrated logic circuits;Bryant,1981

5. Combinational static CMOS networks;Brzozowski;INTEGRATION the VLSI j.,1987

Cited by 2 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. Using Nuprl for the verification and synthesis of hardware;Philosophical Transactions of the Royal Society of London. Series A: Physical and Engineering Sciences;1992-04-15

2. Formal theories and software systems: Fundamental connections between Computer Science and Logic;Lecture Notes in Computer Science

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