Modeling the interface traps-related low frequency noise in triple-gate SOI junctionless nanowire transistors-Reference-Cited by-同舟云学术

Modeling the interface traps-related low frequency noise in triple-gate SOI junctionless nanowire transistors

Published:2019-07 Issue: Volume:215 Page:111005
ISSN:0167-9317
Container-title:Microelectronic Engineering
language:en
Short-container-title:Microelectronic Engineering

Author:

Trevisoli Renan^ORCID,Doria Rodrigo Trevisoli,Barraud Sylvain,Pavanello Marcelo Antonio

Funder

Brazilian Funding Agencies CAPES

CNPq

São Paulo Research Foundation

Publisher

Elsevier BV

Subject

Electrical and Electronic Engineering,Surfaces, Coatings and Films,Condensed Matter Physics,Atomic and Molecular Physics, and Optics,Electronic, Optical and Magnetic Materials

Reference18 articles.

1. FinFETs and Other Multi-Gate Transistors;Colinge,2008

2. Nanowire transistors without junctions;Colinge;Nat. Nanotechnol.,2010

3. SOI gated resistor: CMOS without junctions;Colinge,2009

4. Junctionless multigate field-effect transistor;Lee;Appl. Phys. Lett.,2009

5. Gate-all-around Junctionless nanowire MOSFET with improved low-frequency noise behavior;Singh;IEEE Electron Device Lett.,2011

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