Author:
Mahapatra S.,Alam M.A.,Kumar P. Bharath,Dalei T.R.,Varghese D.,Saha D.
Subject
Electrical and Electronic Engineering,Surfaces, Coatings and Films,Condensed Matter Physics,Atomic and Molecular Physics, and Optics,Electronic, Optical and Magnetic Materials
Reference14 articles.
1. Negative bias temperature instability: road to cross in deep sub-micron silicon semiconductor manufacturing;Schroder;J. Appl. Phys.,2003
2. K. Uwasawa, T. Yamamoto, and T. Mogami, A new degradation mode of scaled p+ polysilicon gate p-MOSFETs induced by bias temperature instability, in: Proc., IEDM, (1995) 871-874
3. N. Kimizuka et. al., The impact of bias temperature instability for direct tunneling ultra-thin gate oxide on MOSFET scaling, in: Proc., VLSI Tech., (1999) 73-74
4. S. Mahapatra and M.A. Alam, A predictive reliability model for PMOS bias temperature degradation, in: Proc., IEDM, (2002) 505-509
5. S. Mahapatra, P. Bharath Kumar and M.A. Alam, A new observation of enhanced bias temperature instability in thin gate oxide p-MOSFETs, in: Proc., IEDM, (2003) 337-340
Cited by
39 articles.
订阅此论文施引文献
订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献