Low-temperature (≤550 °C) p-channel Schottky barrier SOI FinFETs for monolithic 3D integration

Author:

Mao Shujuan,Gao Jianfeng,He Xiaobing,Liu Weibing,Zhou Na,Luo Yanna,Cao Lei,Hu Yanpeng,Zhang Yongkui,Liu Jinbiao,Wang Guilei,Li Tingting,Wu Zhenhua,Li Yongliang,Li Junfeng,Luo Jun,Zhao Chao,Wang Wenwu,Yin Huaxiang

Funder

Beijing Natural Science Foundation

National Natural Science Foundation of China

Youth Innovation Promotion Association of the Chinese Academy of Sciences

Publisher

Elsevier BV

Subject

Electrical and Electronic Engineering,Surfaces, Coatings and Films,Condensed Matter Physics,Atomic and Molecular Physics, and Optics,Electronic, Optical and Magnetic Materials

Reference19 articles.

1. Monolithic 3D: An alternative to advanced CMOS scaling, technology perspectives and associated design methodology challenges;Vivet,2018

2. Key process steps for high performance and reliable 3D sequential integration;Lu,2017

3. Sequential 3D: key integration challenges and opportunities for advanced semiconductor scaling;Vandooren,2018

4. Footprint-efficient and power-saving monolithic IoT 3D+ IC constructed by BEOL-compatible Sub-10 nm high Aspec ratio (AR>7) single-grained Si FinFETs with record high ion of 0.38 mA/μm and steep-swing of 65 mV/dec. and ion/Ioff ratio of 8;Yang,2016

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