Overlay as the key to drive wafer scale 3D integration-Reference-Cited by-同舟云学术

Overlay as the key to drive wafer scale 3D integration

Published:2007-05 Issue:5-8 Volume:84 Page:1412-1415
ISSN:0167-9317
Container-title:Microelectronic Engineering
language:en
Short-container-title:Microelectronic Engineering

Author:

Steen Steven E.,LaTulipe Douglas,Topol Anna W.,Frank David J.,Belote Kevin,Posillico Dominick

Publisher

Elsevier BV

Subject

Electrical and Electronic Engineering,Surfaces, Coatings and Films,Condensed Matter Physics,Atomic and Molecular Physics, and Optics,Electronic, Optical and Magnetic Materials

Reference15 articles.

1. S.J. Abou-Samra, et.al., 3D CMOS SOI for high performance computing, in: Proceedings of the International Symposium on Low Power Electronics and Design (ISLPED), 1998, pp. 54–58.

2. Creating 3D circuits using transferred films

3. S.C. Sun, Process technologies for advanced metallization and interconnect systems, IEDM Tech. Digest, 1997, pp. 765–768.

4. First-Order Performance Prediction of Cache Memory with Wafer-Level3D Integration

5. Three-Dimensional Integrated Circuits and the Future of System-on-Chip Designs

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