A drain leakage phenomenon in poly silicon channel 3D NAND flash caused by conductive paths along grain boundaries

Author:

Wang Bo,Gao BinORCID,Wu Huaqiang,Qian He

Funder

MOST

Beijing Municipal Science and Technology Project

GigaDevice Semiconductor Inc.

Publisher

Elsevier BV

Subject

Electrical and Electronic Engineering,Surfaces, Coatings and Films,Condensed Matter Physics,Atomic and Molecular Physics, and Optics,Electronic, Optical and Magnetic Materials

Reference10 articles.

1. NAND flash memory revolution;Aritome,2016

2. Bit cost scalable technology with punch and plug process for ultra high density flash memory;Tanaka,2007

3. Pipe-shaped BiCS flash memory with 16 stacked layers and multi-level-cell operation for ultra high density storage devices;Katsumata,2009

4. Vertical cell array using TCAT (terabit cell array transistor) technology for ultra high density NAND flash memory;Jang,2009

5. Statistical characterization of vertical poly-Si channel using charge pumping technique for 3D flash memory optimization;Baojun Tang;Microelectron. Eng.,2013

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