Experimental studies of board-level reliability of chip-scale packages subjected to JEDEC drop test condition-Reference-Cited by-同舟云学术

Experimental studies of board-level reliability of chip-scale packages subjected to JEDEC drop test condition

Published:2006-02 Issue:2-4 Volume:46 Page:645-650
ISSN:0026-2714
Container-title:Microelectronics Reliability
language:en
Short-container-title:Microelectronics Reliability

Author:

Lai Yi-Shao,Yang Ping-Feng,Yeh Chang-Lin

Publisher

Elsevier BV

Subject

Electrical and Electronic Engineering,Surfaces, Coatings and Films,Safety, Risk, Reliability and Quality,Condensed Matter Physics,Atomic and Molecular Physics, and Optics,Electronic, Optical and Magnetic Materials

Reference11 articles.

1. JEDEC Solid State Technology Association. JESD22-B110: subassembly mechanical shock; 2001.

2. JEDEC Solid State Technology Association. JESD22-B111: board level drop test method of component for handheld electronics products; 2003.

3. Luan J-E, Tee TY, Pek E, Lim CT, Zhong Z. Modal analysis and dynamic responses of board level drop test. In: Proc 5th Electr Pack Technol Conf, Singapore; 2003. p. 233–43.

4. Impact life prediction modeling of TFBGA packages under board level drop test;Tee;Microelectron Reliab,2004

5. Tee TY, Luan J-E, Pek E, Lim CT, Zhong Z. Advanced experimental and simulation techniques for analysis of dynamic responses during drop impact. In: Proc 54th Electr Comp Technol Conf, Las Vegas, NV; 2004. p. 1088–94.

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