Characterizing a RISC-V SRAM-based FPGA implementation against Single Event Upsets using fault injection-Reference-Cited by-同舟云学术

Characterizing a RISC-V SRAM-based FPGA implementation against Single Event Upsets using fault injection

Published:2017-11 Issue: Volume:78 Page:205-211
ISSN:0026-2714
Container-title:Microelectronics Reliability
language:en
Short-container-title:Microelectronics Reliability

Author:

Ramos Alexis^ORCID,Maestro Juan Antonio,Reviriego Pedro

Funder

Spanish Ministry of Economy and Competitiveness

Publisher

Elsevier BV

Subject

Electrical and Electronic Engineering,Surfaces, Coatings and Films,Safety, Risk, Reliability and Quality,Condensed Matter Physics,Atomic and Molecular Physics, and Optics,Electronic, Optical and Magnetic Materials

Reference45 articles.

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2. FPGAs and Parallel Architectures for Aerospace Applications: Soft Errors and Fault-Tolerant Design;Kastensmidt,2016

3. The Cibola flight experiment;Quinn;ACM Trans. Reconfigurable Technol. Syst.,2015

4. Single Event Effects in Aerospace;Petersen,2011

5. Evaluating the effects of SEUs affecting the configuration memory of an SRAM-based FPGA;Bellato,2004

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