An Efficient Fault-Tolerant Instruction Decoder for RISC-V Based Dual-Core Soft-Processors-Reference-Cited by-同舟云学术

An Efficient Fault-Tolerant Instruction Decoder for RISC-V Based Dual-Core Soft-Processors

Published:2023-12 Issue:12 Volume:70 Page:4816-4825
ISSN:1549-8328
Container-title:IEEE Transactions on Circuits and Systems I: Regular Papers
language:
Short-container-title:IEEE Trans. Circuits Syst. I

Author:

Shukla Satyam¹^ORCID,Utkarsh ¹^ORCID,Azam Md¹,Ray Kailash Chandra¹^ORCID

Affiliation:

1. Department of Electrical Engineering, Indian Institute of Technology Patna, Patna, Bihar, India

Funder

Ministry of Electronics and Information Technology, Government of India, New Delhi, through the project titled “Special Manpower Development Program for Chips to System Design,”

Visvesvaraya Ph.D. Scheme

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

Electrical and Electronic Engineering,Hardware and Architecture

Link

http://xplorestaging.ieee.org/ielx7/8919/10363413/10260708.pdf?arnumber=10260708

Reference44 articles.

1. Single-Event Multiple Effect Tolerant RHBD14T SRAM Cell Design for Space Applications

2. Highly Stable Low Power Radiation Hardened Memory-by-Design SRAM for Space Applications

3. A Scheme to Design Concurrent Error Detection Techniques for the Fast Fourier Transform Implemented in SRAM-Based FPGAs

4. Single Event Effects in Aerospace

5. Single Event Phenomena I

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