An automated approach for locating multiple faulty LUTs in an FPGA-Reference-Cited by-同舟云学术

An automated approach for locating multiple faulty LUTs in an FPGA

Published:2008-11 Issue:11-12 Volume:48 Page:1900-1906
ISSN:0026-2714
Container-title:Microelectronics Reliability
language:en
Short-container-title:Microelectronics Reliability

Author:

Nandha Kumar T.,Chong Chia Wai

Publisher

Elsevier BV

Subject

Electrical and Electronic Engineering,Surfaces, Coatings and Films,Safety, Risk, Reliability and Quality,Condensed Matter Physics,Atomic and Molecular Physics, and Optics,Electronic, Optical and Magnetic Materials

Reference18 articles.

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3. Abramovici M, Stroud C. BIST-based detection and diagnosis of multiple faults in FPGAs. In: Proceedings of the IEEE international test conference; 2000. p. 785–94.

4. Huang WK, Lobardi F. A general technique for testing FPGA’s. In: Proceedings of the IEEE VLSI test symposium; 1996. p. 450–5.

5. Testing configurable LUT based FPGA;Huang;IEEE Trans VLSI Syst,1998

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