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A novel BRAM content accessing and processing method based on FPGA configuration bitstream

  • Published:2017-03 Issue: Volume:49 Page:64-76
  • ISSN:0141-9331
  • Container-title:Microprocessors and Microsystems
  • language:en
  • Short-container-title:Microprocessors and Microsystems

Author:

Gomez-Cornejo J.,Zuloaga A.,Villalta I.,Del Ser J.ORCID,Kretzschmar U.,Lazaro J.

Publisher

Elsevier BV

Subject

Artificial Intelligence,Computer Networks and Communications,Hardware and Architecture,Software

Reference57 articles.

1. Xilinx Corp., Zynq-7000 all programmable SoC technical reference manual UG585 (v1.9.1), 2014, (Xilinx Documentation, http://www.xilinx.com).

2. Xilinx implementation tutorial;Bales,2007

3. Basic mechanisms and modeling of single-event upset in digital microelectronics;Dodd;IEEE Trans. Nucl. Sci.,2003

4. SEU recovery mechanism for SRAM-based FPGAs;Legat;IEEE Trans. Nucl. Sci.,2012

5. Analysis of SET effects in a PIC microprocessor for selective hardening;Entrena;IEEE Trans. Nucl. Sci.,2011

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1. A Review on Soft Error Correcting Techniques of Aerospace-Grade Static RAM-Based Field-Programmable Gate Arrays;Sensors;2024-08-19

2. A New Methodology to Manage FPGA Distributed Memory Content via Bitstream for Xilinx ZYNQ Devices;Electronics;2022-12-27

3. Data content scrubbing approach for SRAM based FPGA designs;2022 IEEE 31st International Symposium on Industrial Electronics (ISIE);2022-06-01

4. XBERT: Xilinx Logical-Level Bitstream Embedded RAM Transfusion;2021 IEEE 29th Annual International Symposium on Field-Programmable Custom Computing Machines (FCCM);2021-05

5. Multiple Cell Upset Injection in BRAMs for Xilinx FPGAs;IEEE Transactions on Device and Materials Reliability;2018-12
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