A generalized modular redundancy scheme for enhancing fault tolerance of combinational circuits

Author:

El-Maleh Aiman H.,Oughali Feras Chikh

Publisher

Elsevier BV

Subject

Electrical and Electronic Engineering,Surfaces, Coatings and Films,Safety, Risk, Reliability and Quality,Condensed Matter Physics,Atomic and Molecular Physics, and Optics,Electronic, Optical and Magnetic Materials

Reference14 articles.

1. Mohanram K, Touba NA. Partial error masking to reduce soft error failure rate in logic circuits. In: Proceedings 18th IEEE international symposium on defect and fault tolerance in VLSI systems, November 2003. p. 433–40.

2. Krishnaswamy S, Plaza SM, Markov IL, Hayes JP. Enhancing design robustness with reliability-aware resynthesis and logic simulation. In: IEEE/ACM international conference on computer-aided design, ICCAD 2007, November. 2007. p. 149–54.

3. She Xiaoxuan, Samudrala PK. Selective triple modular redundancy for single event upset (SEU) mitigation. In: NASA/ESA conference on adaptive hardware and systems, AHS 2009, August 2009. p. 344–50.

4. Defect-tolerant N2-transistor structure for reliable nanoelectronic designs;El-Maleh;Comput Digital Tech IET,2009

5. Al-Qahtani Ayed Saad. Fault tolerance techniques for sequential circuits: a design level approach. Master’s thesis. King Fahd University of Petroleum & Minerals, June 2010.

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