Enhancing design robustness with reliability-aware resynthesis and logic simulation
Author:
Publisher
IEEE
Link
http://xplorestaging.ieee.org/ielx5/4397222/4397223/04397258.pdf?arnumber=4397258
Cited by 26 articles. 订阅此论文施引文献 订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献
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3. Increasing the Accuracy of Reliability-aware Resynthesis with Standard Cell Reliability Characterization;2021 IEEE Conference of Russian Young Researchers in Electrical and Electronic Engineering (ElConRus);2021-01-26
4. A Hierarchical Scrubbing Technique for SEU Mitigation on SRAM-Based FPGAs;IEEE Transactions on Very Large Scale Integration (VLSI) Systems;2020-10
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