New insight on negative bias temperature instability degradation with drain bias of 28nm High-K Metal Gate p-MOSFET devices

Author:

Liao Miao,Gan Zhenghao

Publisher

Elsevier BV

Subject

Electrical and Electronic Engineering,Surfaces, Coatings and Films,Safety, Risk, Reliability and Quality,Condensed Matter Physics,Atomic and Molecular Physics, and Optics,Electronic, Optical and Magnetic Materials

Reference11 articles.

1. Krishnan AT, Reddy V, Chakravarthi S, Rodriguez J, John S, Krishnan S. NBTI impact on transistor and circuit: models, mechanisms, and scaling effect. In: IEDM Tech Dig 2003; p. 349–52.

2. Impact of NBTI on the temporal performance degradation of digital circuits;Paul;IEEE Electron Device Lett,2005

3. He Y, Zhang G. Experimental insights on the degradation and recovery of pMOSFET under non-uniform NBTI stresses. In: Proc. IEEE Int. Symp Phys Failure Anal Integr Circuits 2011; p. 1–6.

4. Anomalous negative bias temperature instability degradation induced by source/drain bias in nanoscale PMOS devices;Yan;IEEE Trans Nanotechnol,2008

5. Federspiel X, Rafik M, Angot D, Cacho F, Roy D. Interaction between BTI and HCI degradation in High-K devices. In: Proc Int Rel Phys Symp 2013; p. XT.9.1–XT.9.4.

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