Anomalous Negative Bias Temperature Instability Degradation Induced by Source/Drain Bias in Nanoscale PMOS Devices-Reference-Cited by-同舟云学术

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Anomalous Negative Bias Temperature Instability Degradation Induced by Source/Drain Bias in Nanoscale PMOS Devices

Published:2008-07 Issue:4 Volume:7 Page:418-421
ISSN:1536-125X
Container-title:IEEE Transactions on Nanotechnology
language:
Short-container-title:IEEE Trans. Nanotechnology

Author:

Baoguang Yan ,Jingfeng Yang ,Zhiliang Xia ,Xiaoyan Liu ,Gang Du ,Ruqi Han ,Jinfeng Kang ,Liao C.C.,Zhenghao Gan ,Miao Liao ,Wang J.P.,Waisum Wong

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

Electrical and Electronic Engineering,Computer Science Applications

Link

http://xplorestaging.ieee.org/ielx5/7729/4578722/04531757.pdf?arnumber=4531757

Cited by 3 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. Negative gate bias stress effects on conduction and low frequency noise characteristics in p-type poly-Si thin-film transistors*;Chinese Physics B;2019-08-01

2. New insight on negative bias temperature instability degradation with drain bias of 28nm High-K Metal Gate p-MOSFET devices;Microelectronics Reliability;2014-11

3. A New Model for Two-Dimensional Electrical-Field-Dependent $V_{\rm th}$ Instability of pMOSFETs With Ultrathin DPN Gate Dielectrics;IEEE Electron Device Letters;2011-05

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