Real-world printed circuit board ESD failures-Reference-Cited by-同舟云学术

Real-world printed circuit board ESD failures

Published:2005-02 Issue:2 Volume:45 Page:287-295
ISSN:0026-2714
Container-title:Microelectronics Reliability
language:en
Short-container-title:Microelectronics Reliability

Author:

Olney Andrew,Gifford Brad,Guravage John,Righter Alan

Publisher

Elsevier BV

Subject

Electrical and Electronic Engineering,Surfaces, Coatings and Films,Safety, Risk, Reliability and Quality,Condensed Matter Physics,Atomic and Molecular Physics, and Optics,Electronic, Optical and Magnetic Materials

Reference16 articles.

1. ESD myths and the latency controversy;Dangelmayer;Compl. Eng.,2002

2. The most common causes of ESD damage;Peirce;Eval. Eng.,2002

3. Chip-level charged-device modeling and simulation in CMOS integrated circuits;Lee;IEEE Trans. Comput.-Aid. Design Integrated Circ. Syst.,2003

4. Barth J, Richner J, Verhaege K, Kelly M, Henry LG. Correlation considerations II: real HBM to HBM testing. In: EOS/ESD Symposium Proceedings, EOS-24; 2002. p. 155–62

5. Olney A. A combined socketed and non-socketed CDM test approach for eliminating real-world CDM failures. In: EOS/ESD Symposium Proceedings, EOS-18; 1996. p. 62–75

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