Study of thinned Si wafer warpage in 3D stacked wafers-Reference-Cited by-同舟云学术

Study of thinned Si wafer warpage in 3D stacked wafers

Published:2010-12 Issue:12 Volume:50 Page:1988-1993
ISSN:0026-2714
Container-title:Microelectronics Reliability
language:en
Short-container-title:Microelectronics Reliability

Author:

Kim Youngrae,Kang Sung-Keun,Kim Sarah Eunkyung

Publisher

Elsevier BV

Subject

Electrical and Electronic Engineering,Surfaces, Coatings and Films,Safety, Risk, Reliability and Quality,Condensed Matter Physics,Atomic and Molecular Physics, and Optics,Electronic, Optical and Magnetic Materials

Reference13 articles.

1. List RS, Webb C, Kim SE. 3D Wafer stacking technology. In: Proc of AMC; 2002. p. 29–36.

2. Ultra-thin semiconductor wafer applications and process;Gurnett;Adv Semicond Mag,2006

3. Modern IC packaging trends and their reliability implications;Plieninger;Microelectron Reliab,2006

4. Morrow P, Kobrinsky M, Harmes M, Park C, Ramanathan S, Ramachandrarao V, et al. Wafer-Level 3D Interconnects Via Cu Bonding. In: Proc of AMC, vol. 20; 2004. p. 125–30.

5. Wafer-level package interconnect options;Balachandran;IEEE VLSI Syst,2006

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