A defect-oriented test approach using on-Chip current sensors for resistive defects in FinFET SRAMs

Author:

Medeiros G.C.,Bolzani Poehls L.M.,Taouil M.,Luis Vargas F.,Hamdioui S.

Funder

European Union's Horizon 2020

Publisher

Elsevier BV

Subject

Electrical and Electronic Engineering,Surfaces, Coatings and Films,Safety, Risk, Reliability and Quality,Condensed Matter Physics,Atomic and Molecular Physics, and Optics,Electronic, Optical and Magnetic Materials

Reference29 articles.

1. Technology and design challenges for low power and high performance;De,1999

2. Multigate transistors as the future of classical metal–oxide–semiconductor field-effect transistors;Ferain;Nature,2011

3. Leakage current mechanisms and leakage reduction techniques in deep-submicrometer CMOS circuits;Roy;Proc. IEEE,2003

4. Considerations for ultimate CMOS scaling;Kuhn;IEEE Trans. Electron Devices,2012

5. Basics on SRAM Testing;Girard,2010

Cited by 6 articles. 订阅此论文施引文献 订阅此论文施引文献,注册后可以免费订阅5篇论文的施引文献,订阅后可以查看论文全部施引文献

1. H2C-TM: A Hybrid High Coverage Test Method for Improving the Detection of HtD Faults in STT-MRAMs;IEEE Transactions on Device and Materials Reliability;2023-06

2. LCHC-DFT: A Low-Cost High-Coverage Design-for-Testability Technique to Detect Hard-to-Detect Faults in STT-MRAMs in the Presence of Process Variations;IEEE Transactions on Device and Materials Reliability;2022-12

3. CD-DFT: A Current-Difference Design-for-Testability to Detect Short Defects of STT-MRAM Under Process Variations;IEEE Transactions on Device and Materials Reliability;2021-09

4. Hard-to-Detect Fault Analysis in FinFET SRAMs;IEEE Transactions on Very Large Scale Integration (VLSI) Systems;2021-06

5. Detecting Random Read Faults to Reduce Test Escapes in FinFET SRAMs;2021 IEEE European Test Symposium (ETS);2021-05-24

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