Memoryless nonlinearity in IT JL FinFET with spacer technology: Investigation towards reliability

Author:

Vandana B.,Mohapatra S.K.,Das J.K.,Pradhan K.P.,Kundu A.,Kaushik B.K.

Publisher

Elsevier BV

Subject

Electrical and Electronic Engineering,Surfaces, Coatings and Films,Safety, Risk, Reliability and Quality,Condensed Matter Physics,Atomic and Molecular Physics, and Optics,Electronic, Optical and Magnetic Materials

Reference34 articles.

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4. Novel high-κ dielectrics for next-generation electronic devices screened by automated ab initio calculations;Yim;NPG Asia Mater.,2015

5. Sidewall spacer optimization for steep switching junctionless transistors;Gupta;Semicond. Sci. Technol.,2016

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3. Temperature Dependent Linearity/Harmonic Analysis for FinFET and Gate All Around (GAA) Nanowire FET;2021 IEEE 2nd International Conference on Applied Electromagnetics, Signal Processing, & Communication (AESPC);2021-11-26

4. Insulated Shallow Extension Dual Metal Junctionless Accumulation Mode MOSFET (ISE-DMJAM-MOSFET);2021 IEEE 2nd International Conference on Applied Electromagnetics, Signal Processing, & Communication (AESPC);2021-11-26

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