Impact and damage on deep sub-micron CMOS technology induced by substrate current due to ESD stress

Author:

Galy Ph.,Dudit S.,Vallet M.,Richier C.,Entringer C.,Jezequel F.,Petit E.,Beltritti J.

Publisher

Elsevier BV

Subject

Electrical and Electronic Engineering,Surfaces, Coatings and Films,Safety, Risk, Reliability and Quality,Condensed Matter Physics,Atomic and Molecular Physics, and Optics,Electronic, Optical and Magnetic Materials

Reference12 articles.

1. Smedes T. On the relevance of IC ESD performance to product quality. In: EOS/ESD symposium; 2008. p. 14–20.

2. Perdu P. Advanced failure analysis with respect to ESD failures. In: 2nd International ESD workshop IEW; 2008. p. 23–47.

3. Esmark K et al. Advanced 2D/3D ESD device simulation – a powerful tool already used in a pre-si phase. In: EOS/ESD symposium; 2000. p. 420–9.

4. Karp J et al. Effect of flip chip package parameters on CDM discharge. In: EOS/ESD symposium; 2008. p. 1–5.

5. Gao Y et al. Modeling of the substrate resistance in high injection for CDM circuit level simulation. In: 2th IEW; 2008. p. 470–7.

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