Clock aligner based on delay locked loop with double edge synchronization-Reference-Cited by-同舟云学术

Clock aligner based on delay locked loop with double edge synchronization

Published:2008-01 Issue:1 Volume:48 Page:158-166
ISSN:0026-2714
Container-title:Microelectronics Reliability
language:en
Short-container-title:Microelectronics Reliability

Author:

Stojčev Mile,Jovanović Goran

Publisher

Elsevier BV

Subject

Electrical and Electronic Engineering,Surfaces, Coatings and Films,Safety, Risk, Reliability and Quality,Condensed Matter Physics,Atomic and Molecular Physics, and Optics,Electronic, Optical and Magnetic Materials

Reference23 articles.

1. Digital system clocking: high-performance and low-power aspects;Oklobdzija,2003

2. Timing;Sapatnekar,2004

3. High-speed signal propagation: advanced black magic;Johnson,2003

4. Clocking and clocked storage elements in a multi-gigahertz environment;Oklobdzija;IBM J Res Dev,2003

5. Phase-locking in high-performance systems: from devices to architectures;Razavi,2003

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