1. A 5.67mW 9Gb/s DLL-based reference-less CDR with pattern-dependent clock-embedded signaling for intra-panel interface;Baek;IEEE ISSCC Dig. Tech. Papers,2014
2. A 140-Mb/s to 1.82-Gb/s continuous-rate embedded clock receiver for flat-panel displays;Jung;IEEE Trans. Circuits Syst. II, Exp. Briefs,2009
3. 12Gb/s over four balanced lines utilizing NRZ braid clock signaling with 100% data payload and spread transition scheme for 8K UHD intra-panel interfaces;Lee;IEEE ISSCC Dig. Tech. Papers,2017
4. A 13.8mW 3.0Gb/s clock-embedded video interface with DLL-based data-recovery circuit;Jang;IEEE ISSCC Dig. Tech. Papers,2011
5. A 2.0Gb/s clock-embedded interface for full-HD 10b 120Hz LCD drivers with 1/5-rate noise-tolerant phase and frequency recovery;Yamaguchi;IEEE ISSCC Dig. Tech. Papers,2009