A 0.13-μm CMOS resonator-based frequency-doubling mechanism for clock recovery in a full-rate 40 Gb/s optical receiver
Author:
Funder
Institute for Information and Communications Technology Promotion
Ministry of Science, ICT and Future Planning
Publisher
Elsevier BV
Subject
General Engineering
Reference14 articles.
1. A 32-Gb/s PAM-4 quarter-rate clock and data recovery circuit with an input slew-rate tolerant selective transition detector;Kwon;IEEE Transactions on Circuits and Systems II: Express Briefs,2019
2. A 56-Gb/s PAM4 receiver with low-overhead techniques for threshold and edge-based DFE FIR- and IIR-tap adaptation in 65-nm CMOS;Roshan-Zamir;IEEE J. Solid State Circ.,2019
3. A pattern-dependent injection-locked CDR for clock-embedded signaling;Hong;Microelectron. J.,2020
4. Innovative 28 Gb/s quarter rate receiver with data-rate-tolerant adaptive continuous-time linear equalizer;Han;Microelectron. J.,2021
5. Analysis and modeling of the phase detector hysteresis in bang-bang PLLs;Bashiri;IEEE Transactions on Circuits and Systems I: Regular Papers,2015
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