Main degradation mechanism in AsTeGeSiN threshold switching devices

Author:

Choi Hyun-Sik

Funder

Chosun University

Publisher

Elsevier BV

Subject

Electrical and Electronic Engineering,Surfaces, Coatings and Films,Safety, Risk, Reliability and Quality,Condensed Matter Physics,Atomic and Molecular Physics, and Optics,Electronic, Optical and Magnetic Materials

Reference13 articles.

1. A highly scalable vertical gate (VG) 3D NAND Flash with robust program disturb immunity using a novel PN diode decoding structure;Hung,2011

2. A stacked memory device on logic 3D technology for ultra-high-density data storage;Kim;Nanotechnology,2011

3. Circuit and microarchitecture evaluation of 3D stacking magnetic RAM (MRAM) as a universal memory replacement;Dong,2008

4. A fast, high-endurance and scalable non-volatile memory device made from asymmetric Ta2O5−x/TaO2−x bilayer structures;Lee;Nat. Mater.,2011

5. A 20nm 1.8V 8Gb PRAM with 40Mb/s program bandwidth;Choi,2012

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1. Memory Challenges;Springer Handbook of Semiconductor Devices;2022-11-11

2. Ge-Se-Sb-N-based OTS scaling perspectives for high-density 1 S1R crossbar arrays;2021 IEEE International Memory Workshop (IMW);2021-05

3. Different degradation mechanism by conduction region in AsTeGeSiN threshold switching device;Electronics Letters;2020-09-25

4. Crosspoint Memory Arrays: Principle, Strengths and Challenges;2020 IEEE International Memory Workshop (IMW);2020-05

5. Downscaling AsTeGeSiN threshold switching devices for high‐density 3D memories;IET Circuits, Devices & Systems;2018-04-17

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