A technique to mitigate impact of process, voltage and temperature variations on design metrics of SRAM Cell-Reference-Cited by-同舟云学术

A technique to mitigate impact of process, voltage and temperature variations on design metrics of SRAM Cell

Published:2012-02 Issue:2 Volume:52 Page:405-411
ISSN:0026-2714
Container-title:Microelectronics Reliability
language:en
Short-container-title:Microelectronics Reliability

Author:

Islam A.,Hasan Mohd.

Publisher

Elsevier BV

Subject

Electrical and Electronic Engineering,Surfaces, Coatings and Films,Safety, Risk, Reliability and Quality,Condensed Matter Physics,Atomic and Molecular Physics, and Optics,Electronic, Optical and Magnetic Materials

Reference16 articles.

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2. Driving source-line cell architecture for sub-1-V high-speed low-power applications;Mizuno;IEEE J Solid-State Circ,1996

3. Nanoscale Integration and Modeling (NIMO) Group, Arizona State University (ASU). .

4. Device and circuit co-design robustness studies in the subthreshold logic for ultralow-power applications for 32nm CMOS;Vaddi;IEEE Trans Electron Dev,2010

5. Understanding the effect of process variations on the delay static and domino logic;Alioto;IEEE Trans Very Large Scale Integr (VLSI) Syst,2010

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