Reference43 articles.
1. Opportunities for nonvolatile memory systems in extreme-scale high performance computing;Vetter;Comput. Sci. Eng.,2015
2. Next Generation Spin Torque Memories.;Kaushik,2017
3. A scaling roadmap and performance evaluation of in-plane and perpendicular MTJ based STT-MRAMs for high-density cache memory;Chun;IEEE J. Solid-State Circuits,2013
4. A survey of architectural approaches for managing embedded DRAM and non-volatile on-chip caches;Mittal;IEEE Trans. Parallel Distrib. Syst.,2014
5. R. Takemura, T. Kawahara, K. Ono, K. Miura, H. Matsuoka, and H. Ohno, “Highly-scalable disruptive reading scheme for Gb-scale SPRAM and beyond,” in IEEE International Memory Workshop (IMW), 2010, pp. 1–2 Seoul, South Korea, 16-19 May, 2010.
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